Solid state electronic memory system for sorting machines

ABSTRACT

A pickup head generates an output pulse for each ferrule and thus each product being sorted by a sorting machine. The train of pulses are fed to a shift register, whereby sensing a bad product causes the shift register to count down at a rate determined by the series of pulses. An ejector is triggered to eject the bad product when it is carried in register with an associated ejector.

United States Patent Elias H. Codding Houston, Tex.

Mar. 7, 1969 Feb. 23, 1971 Mandrel Industries, Inc. Houston, Tex.

Inventor Appl. No. Filed Patented Assignee SOLID STATE ELECTRONIC MEMORY SYSTEM FOR SORTING MACHINES 10 Claims, 5 Drawing Figs.

US. (I 209/74 Int. Cl. B07c 5/342 Field of Search", 209/74,

lll.6,lll.7,74

[56] References Cited UNITED STATES PATENTS 2,770,796 11/1956 Boer 209/74(M) 2,848,107 8/1958 Juengst et al. 209/74(M) 3 ,259,240 7/1966 Schneider 209/74 3,352,417 11/1967 Cutaia 209/74 3,368,672 2/1968 Heaney et al 209/74X Primary Examiner-Allen N. Knowles Attorney-Robert G. Clay ABSTRACT: A pickup head generates an output pulse for each ferrule and thus each product being sorted by a sorting machine. The train of pulses are fed to a shift register, whereby sensing a bad product causes the shift register to count down at a rate determined by the series of pulses. An ejector is triggered to eject the bad product when it is carried in register with an associated ejector.

SI NGLE- SHOT EJECTOR DRIVER PATENTEU H3523 I97] SHEET 2 OF 2 RECORD TIME MB "CONTROL 56 58%??85 EETGEOT 1W 1-. 59 SINGLE- SINGLE- m SINGLE- SHQT SHOT 4O 42 44 46 SHOT +-1 TL P- FLOP 1 J I DWELL COMMON EMITTER DRIVER HEAD- AMPITIFIER OUTPUT k g k k SINGLE-SHOT 56 W SINGLE-SHOT 5s m I TTZ i CLOCKVPULQSE FLlP-FLOP 44 FLlP-FLOP 46 SINGLE'SHOT 62 T INVENTOR.

ELIAS H. CODDING BY Z;

AT TORNE Y S|NGLE-SHOT 66 AND DRIVER CIRCUIT 68 SOLID STATE ELECTRONIC MEMORY SYSTEM FOR SORTING MACHINES BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is related to memory circuits and particularly to a solid state electronic memory system for sorting machines, which system accepts a reject signal and controls a product ejector in synchronism with thespeed at which the product is being conveyed and inspected.

2. Description of the Prior Art A memory system is required in various product sorting machines wherein the product is viewed at one point but cannot be simultaneously ejected at that point since it is within the inspection chamber. Accordingly, 'as the product is conveyed after viewing, a memory system is employed which remembers a bad product as determined by the classifier circuit, and which actuates the ejector device of the sorting machine only at such time as that particular product is in register with the ejector nozzle. Prior art sorting machines wherein the product is singulated and conveyed'in a controlled, individual fashion through the inspection chamber thereof, generally use a rotating capacitor type of memory circuit, a magnetic tape memory, etc. The rotating capacitor memory system utilize a timer drum with a pluralityof pairs of contacts disposed about respective circumferences of the drum wherein capacitors are connected across the pairs of contacts. The timer drum is rotated by the product conveying drum and a charge is bad on the capacitors when a cull or bad product is viewed. As the drums rotate the capacitor is discharged and fires the ejector at the time the bad product is in register with the ejector. A typical prior art rotating capacitor memory system is shown and described in U.S. Pat. Nos. 2,625,265 issued Jan. 13, 1953, and 2,244,826 issued Jun. 10, 1941, both to DC. Cox. These prior art memory systems are unduly susceptible to wear and arelimited to their use with high speed rotating sorting machines since they are susceptible to the effects of centrifugal force inherent in high speed sorters.

Likewise, magnetic tape or drum memory systems are subject to wear and provide the disadvantage of requiring additional mechanical mechanism (e.g., a magnetic drum, write and read heads, and belt coupling to the sorter drum), in order to rotate the drums in synchronism. The belt coupling causes positional jitter. In addition, in tape or drum memory systems both the applied pulse and the pulse read from the tape vary extensively with the gap between the pickup head and the tape. To improve the readout pulse, the gap is made very small which thus requires high precision design and assembly of the rotating drum or tape assembly. This precision also deteriorates with wear.

SUMMARY OF THE INVENTION The present invention provides a solid state memory system wherein an associated metallic slug is disposed in relation to the means for holding each product which is being sorted; i.e., there is one slug for each product retaining ferrule of the sorting machine. A pickup head capable of sensing the metallic slugs generates an output pulse for each slug and thus for each ferrule or each product. The pulses define clock pulses which operate a series of flip-flops forming a shift register, wherein one flip-flop is employed for each ferrule disposed between the inspection point and the point of ejection. An output from the classifier circuit, indicating a bad product has been viewed, changes the state of the first flip-flop, and the following flip-flops thereafter likewise change state at a rate determined by the clock pulses from the pickup head. The ejector is triggered when the last flip-flop changes state, to eject the bad product which is then in register with the ejector nozzle. Thus variations in the speed of rotation of the sorting drum caused, for example, by power line input variation, etc. are compensated, since the cloclt pulses are supplied at a rate determined by the instantaneous velocity of the drum.

The invention provides a memory system which is formed of solid state components and thus is compatible with a high speed, singulated product, type sorting machine. The system does not impose any speed restrictions on the sorting machine since centrifugal force is of no consequence, and also eliminates wear problems connected for example with the mechanical components of the above mentioned prior art memory system. The more sophisticated embodiment of the invention provides the features of variable record times and variable ejector pulse position and duration.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2A--H is a graph showing a series of wave forms which depict the timing sequence of the circuit of FIG. 1.

FIG. 3 is a simplified perspective view of alternative apparatus for use in the invention system.

FIG. 4 is a block diagram of an alternative embodiment of the present invention.

FIG. 5AL is a graph showing a series of wave forms which depict the timing sequence of the circuit of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG; 1 there is shown a memory system 10 for sorting machines, wherein the adjunct portions of the sorting machine are depicted in simplified configuration and comprise, a drum 12 having a plurality of equally spaced ferrules l4 protruding radially from the periphery of at exact spaced intervals, and an ejector device 16 disposed relative to the periphery of the drum to provide a blast of air at or across a selected ferrule 14' and thus at a product 18 of a series of products 18, a selected distance from the point of inspection. An inspection chamber 20 is disposed about the periphery of the drum 12 to view the productspassing therethrough on their respective ferrules, wherein an output is generated via the inspection chamber 20 and is introduced to an (amplifier) classifier circuit 22 at such time as a bad product is sensed. Although a particular sorting machine apparatus is herein depicted by way of example, many varieties of sorting machines are known in the art with components analogous to those portrayed herein, wherein the invention may be employed. Typical of such sorting machines are those shown for example in the above-mentioned U.S. patents. V

In association therewith, the present invention provides a series of metallic slugs 24 preferrably embedded within the drum 12 along a path concentric about the drum axis, wherein one slug is placed in the drum for each ferrule 14 to define a lto-l relationship. A variable reluctance pickup head 26 is secured in the concentric path of the series of slugs 24 adjacent to the drum. The pickup head 26 is mounted in magnetically coupled relation to the drum I2, preferrably by means of a translatable mounting means 28 adapted to allow adjustment of the head 26 along the path of the slugs 24. Thus, the phasing of the pulses generated by the pickup head 26 upon passage of a metallic slug 24 thereby may be adjusted relative to the ferrules 14 by adjusting the operating position of the head via the mounting means 28. As a slug 24 passes adjacent the pickup head 26 the magnetic path sensed by the head varies causing a change in the voltage on the head and providing an output-pulse therefrom.

It is to be understood that although metallic slugs 24 are embedded in the drum l2 and are sensed by the variable reluctance pickup head 26, any magnetic sensing device could be used instead. In fact, any apparatus capable of generating an electrical pulse in synchronism with each ferrule may be employed.

For example, as shown in FIG. 3, the slugs 24 could be replaced by holes 29 in the drum, and a light source 31 may be disposed to shine through the holes 29 to impinge phototube means 33 on the opposite side of the drum. Thus a pulse is generated in synchronism with each ferrule 14 as each hole passes the light source 31.

Referring to FIG. 2, the pulses generated by the pickup head 26 are introduced, in turn; to a head amplifier means 30 where they are amplified; to a monostable multivibrator or single-shot fiip-fiop 32 where they are shaped in conventional manner to form a squared pulse; and thence to an (amplifier) buffer 34 which provides added driving current to operate the load coupled thereto as further described below. The resulting pulse train defines clock pulses 36 which are introduced to a shift register 38 formed of a series of bistable multivibrators or flip-flop circuits 40, 42, 44, 46. The shift register 38 preferably provides thus one flip-flop 40-46 for each ferrule 14 which is disposed between the inspection point within the inspection chamber 20 and the ejection point corresponding to the position of the ejector device 16. In the present example of the invention, four ferrules are so disposed and accordingly, four flip-flops are employed. However, any number of flip-flops and ferrules (e.g., or may be used instead if desired. The output of the last flip-flop 46 is introduced to a singleshot, ejector driver means 48 which in turn is connected to the ejector 16 to control same. The means 48 is formed generally of a single-shot flip-flop coupled to a high voltage, power transistor; e.g., a common emitter driver circuit which provides of the order of one-half ampere to drive the ejector device 16.

In operation, referring in addition to FIG. 2, as the drum rotates in the direction shown by arrow 50, a pulse is generated by the pickup head 26 for each slug 24 (and associated ferrule 14) which passes by the head. The pulses are amplified to provide pulses 51 (FIG. 2A), which are shaped, and introduced to the flip-flops 40-46 as the train of clock pulses 36. If the individual products held by the ferrules 14 are indicated as good" products no variation is provided in the output of the inspection chamber 20, and no signal is introduced to the first flip-flop 40 of the shift register 38 via the classifier circuit 22. Thus no output is provided by the last flipflop 46 (shift register 38) and no pulse is fed to the ejector device 16.

However, if a bad product is sensed by the inspection chamber 20. a variation in the output thereof is generated at the time the bad product is viewed and a corresponding signal is fed to the classifier circuit 22. The circuit 22 delivers a pulse 52 (FIG. 2C) to the first fiip-fiop 40 of the shift register 38 in the period of time between two successive clock pulses 36 (FIG. 2B). The pulse 52 (which could be positive or negative depending upon the associated circuitry) causes a change of state in the flip-flop 40 (FIG. 2D) which is maintained until the occurrence of the next clock pulse. Thereafter the flipfiops 42, 44 and 46 will also change-state in a sequence corresponding to the rate of the incoming clock pulses 36 as depicted in FIGS. 2E-2G. When the last flip-flop 46 changes state a signal is introduced to the single-shot ejector driver means 48, whereby a pulse 54 (FIG. 2H) is delivered to the ejector 16 to actuate same. Since the bad product (indicated here as 18) has moved the distance from the inspection point to the ejection point (which distance corresponds to the timing of the sequentially operated flip-flops 40-46) the ejector 16 is actuated at the precise time that the bad product 18 is in register with the ejector l6, and the bad product is ejected. The width of the pulse 54 may be varied by varying the timing constant of the single-shot ejector driver means 48, to provide a longer or shorter operating period for the ejector. This allows matching the energy generated by the ejector to the size and weight of the particular product being sorted; e.g., a longer burst of air is provided for a larger product.

Referring to FIG. 4, there is shown a more sophisticated embodiment of the invention memory system, which provides the additional features of, a variable record time, a variable ejector pulse position (within a preselected ferrule spacing) and a variable ejector pulse duration (e.g., the width of pulse 54 of FIG. 2H). Similar components of the circuits and the sorting machines shown in FIGS. 1 and 4 are similarly numbered.

The head amplifier means is coupled to a pair of controllable, monostable multivibrators or single-shot flip-flops S6, 58, respectively, hereinafter termed single-shots. The singleshots 56, 58 are capable of providing variable width output pulses as regulated by respective potentiometers (indicated at 59) coupled thereto. The potentiometers provide a "record time control; i.e., means for varying the time constant of the single-shots 56, 58. The potentiometers preferable are mechanically ganged together, wherein the delay of singleshot 58 is one-half that of single-shot56 throughout their common range of adjustment. The single-shots 56, 58, as well as the other controllable, single-shots further described hereinafter, are commonly known in the art as controllable single-shot (or monostable) multipliers and thus are not further described herein. The output of single-shot 56 is coupled to a conventional AND gate 60, which is also coupled to the output of the (amplifier) classifier circuit 22. The AND gate 60 inturn is coupled to the shift register 38 and in particular the first bistable flip-flop 40 thereof.

The single-shot 58 is coupled to a single-shot flip-flop 32, which generally corresponds to the single-shot flip-flop 32 of FIG. 1. The single-shot 32 is coupled to the (amplifier) buffer 34 to provide therefrom the train of clock pulses 36 to the plurality of bistable flip-flops 40-46 forming the shift register 38, as previously described with reference to FIG. 1. However, the clock pulses 36 are also introduced to a controllable single-shot flip-flop 62, which in turn is coupled to a second AND gate 64. The shift register 38 output (flip-flop 46 output), is coupled as the second input to the AND gate 64. AND gate 64 is thence coupled to a controllable single-shot flip-flop 66, which is generally analogous to the single-shot flip-flop portion of the ejector driver means 48 of FIG. I, but which is also controllable. The controllable single-shots 62 and 66 have variable time constants and thus variable delays as described with reference to single-shots 56, 58. The output of the singleshot 66 is fed to a common emitter driver circuit 68, where 66, 68 define a controllable, ejector driver means 48. Ejector device 16 is actuated by the driver means 48'.

The circuit of FIG. 4 operates in essentially the same manner as that of FIG. 1, in sensing and' subsequently accurately ejecting a bad product. However, as may be seen from FIG. SA-L, various additional adjustable timing features are available in the invention circuit of FIG. 4. Thus head amplifier pulses 51 (FIG. 5A) are supplied to a controllable singleshots 56, 58 and provide a change of state, i.e., outputs 70, 72 as shown in FIG. 2B, 2C respectively. The delay of single-shot 58 is preferably maintained about one-half of the delay of single-shot 56 throughout the adjustable range thereof, whereby accordingly, the clock pulses 36 (FIG. 5D) always occur in about the middle of the dead time period 73 of the singleshot 56 (FIG. 5B). Thus the potentiometers are mechanically ganged together with the one-half ratio between a "dead time" period 77 (FIG. 5C) and 73 (FIG. 58) whereby varying the extent of delay of the single-shots 56, 58 (and thus the width of of the dead time" period 73 and a record time" period 75, FIG. 58) does not change the ratio, although the clock pulse timing is varied accordingly.

When a bad product is sensed via the inspection chamber 20, classifier circuit 22 feeds a signal 74 (FIG. 5E) indicative of the bad produce to the AND gate 60, which also receives the output 70 from single-shot 56. However, AND gate 60 will not supply an output pulse 76 (FIG. 5F) until such time as the output of the single-shot 56 returns to ground. Note the circuits may be modified whereby positive pulses are utilized. The pulse 76 then is fed to the first flip-flop 40 of the shift register 38, which then counts down in synchronism with the clock pulses 36 and thus the drum 12 velocity as described with respect to FIG. 1, until an output signal is introduced to the AND gate 64 via the last flip-flop 46 (FIG. 5G-5J). The controllable single-shot 62 provides an output signal 78 (FIG. 5K) to the AND gate 64 which in turn provides an output signal to the controllable single-shot 66 and common emitter driver circuit 68. Note the single-shot 66 cannot be triggered until both the single-shot 62 and the flip-flop 46 are positive, at which time the driver circuit 68 provides an ejectro driving pulse 80 (FIG. 5L). Thus, the time delay of the single-shot 62 determines the time (between two consecutive clock pulses 36) that the pulse 80 is generated and that the ejector device 16 begins to operate. The width 82 of the delay delivered by single-shot 62 can be varied as desired, by varying the time constant thereof by a potentiometer (not shown) comprising the ejector pulse position control. Likewise, the width 84 of the delay delivered by the single-shot 66 is controlled by varying the time constant thereof via the divell control potentiometer (not shown) which varies accordingly the duration of the ejector device 16 operation.

It may be seen that the circuit of FIG. 4 provides improved sorting capacity, for example as when sorting larger products of uniform discoloration. in this case it is sufficient to look at the portion of the product directly over the ferrule to judge whether the product is good or bad. Looking" at more of the product, increases the chance of seeing the end of an adjacent bad product, causing the ejection of a possibly good product. Rather than decrease the number of ferrules to overcome the problem, which obviously would reduce the sorting capacity, the invention of FIG. 4 provides the variable record time control via single-shots 56, 58, whereby the ratio of record time" to "dead time" (e.g., FIG. 58) can be adjusted. Thus, the time during which the sorting machine looks at each product can be readily adjusted and controlled by electronic means.

In addition the ejector pulse position control" facilitates setup of the apparatus, as it provides electrical means for adjusting the position of the ejector device 16 along the periphery of the drum 12.

Thus although specific embodiments of the invention are shown herein by way of example, various modifications may be made within the scope of the invention. For example, the invention may be employed in conjunction with a sorting machine which conveys the product in a linear, straight configuration, rather than by means of the rotating drum type of sorter as shown. Also, the s1ugs24 (or holes 29) may be disposed either in register with, or somewhere between, the ferrules 14 of either embodiment, whereby proper phasing is provided as previously noted by adjusting the pickup head 26 (or light source 31 phototube means 33) position via the translatable mounting means 28.

lclaim: l. A memory system for high speed, singulated product, sorting machines having a succession of product retaining means for individually conveying the product past an inspection chamber, including ejector means disposed a selected distance from the-inspection chamber, and a classifier circuit for generating a reject pulse in response to the sensing of a bad product by the inspection chamber, comprising the combination of:

means for providing a series of clock pulses in synchronism with the speed at which the product is being conveyed and inspected, said means for providing a series of clock pulses including means associated with said succession of product retaining means for generating a series of electrical pulses in synchronism with the instantaneous speed of the product retaining means;

shift register means operatively coupled to said classifier circuit and to said means for providing the series of clock pulses, to receive said clock pulses and to generate an output pulse after a selected time delay proportional to the distance between the inspection chamber and the ejector means and determined by the rate of the series of clock pulses, the number of clock pulses being equal to the number of product retaining means disposed between the inspection chamber and said ejection means; and

ejector driver means coupled to said shift register means for introducing a driver pulse to said ejector means in response to the occurrence of the output pulse from the shift register means. 7

2. The memory system of claim 1 wherein the means associated with said succession of product retaining means further includes a slug of magnetic material precisely positroned relative to each of the succession of product retaining means, and magnetic pickup means fixedly disposed to sense the passage of the succession of slugs, and for generating a pulse commensurate with the time each slug passes adjacent the magnetic pickup means.

3. The memory system of claim 1 wherein the means associated with said succession of product retaining means further includes a hole precisely positioned relative to each of the succession of product retaining means, light source means fixedly disposed to direct a beam of light through the succession of holes, and phototube means fixedly disposed to receive the light beam upon passage of each hole past the light source means and to generate said series of electrical pulses in synchronism with the speed of the product retaining means.

4. The memory system of claim 1 wherein said means for providing a series of clock pulses includes amplifying and shaping means coupled to said means associated with said succession of product retaining means for delivering said number of clock pulses to said shift register means in response to the series of electrical pulses.

5. The system of claim 4, wherein said shift register means include a plurality of bistable flip-flop circuits equal to the number of product retaining means disposed between the inspection chamber and the ejector means and connected in series, the flip-flop circuits being coupled to receive the series of clock pulses, wherein a first of the plurality of flip-flop circuits is further operatively coupled to said classifier circuit, and the last of the plurality of flip-flop circuits is operatively coupled to said ejector driver means.

6. The system of claim 5, wherein said classifier circuit provides said reject pulse for subsequent introduction to the first flip-flop circuit when the inspection .chamber senses a bad product to thus change the state of the first flip-flop whereupon the successive flip-flop circuits change state at a rate determined by the successive introduction thereto of said number of clock pulses, said clock pulses being in synchronism with the instantaneous speed of the product retaining means, said last flip-flop circuit providing an output pulse upon changing state.

7. The system of claim 1 wherein the means for providing a series of clock pulses further includes controllable timing means operatively coupled to said shift register means for delivering the series of clock pulses with a controllable time delay relative to the conveyed product.

8. The system of claim 7 further including ejector pulse position controlling means coupled between the means for providing the series of clock pulses and the ejector driver means for controllably varying the initiation of the driver pulse relative to the preceding clock pulse.

9. The system of claim 8 wherein the controllable timing means includes a pair of single-shot multivibrators coupled to receive the series of electrical pulses, gating means coupled to one of said single-shot multivibrators and also to said classifier circuit for delivering a reject output in response to said reject pulse from the classifier circuit and an output from the multivibrator, pulse shaping and amplifying means coupled to the second of the single-shot multivibrators and thence to the shift register means, said pair of single-shot multivibrators having means for controlling the time constants thereof wherein the time constants are maintained at a selected ratio over the controllable range. v

10. The system of claim 9, wherein the ejector pulse position controlling means includes a third single-shot multivibrator coupled to receive the series of clock pulses, and second gating means coupled to the shift register means and to the third single-shot multivibrator for introducing a single signal to said ejector driver means, said third single-shot multivibrator including means for controlling the time constant thereof wherein the signal delivered to the ejector driver means is selectively varied relative to the respective clock pulse. 

1. A memory system for high speed, singulated product, sorting machines having a succession of product retaining means for individually conveying the product past an inspection chamber, including ejector means disposed a selected distance from the inspection chamber, and a classifier circuit for generating a reject pulse in response to the sensing of a bad product by the inspection chamber, comprising the combination of: means for providing a series of clock pulses in synchronism with the speed at which the product is being conveyed and inspected, said means for providing a series of clock pulses including means associated with said succession of product retaining means for generating a series of electrical pulses in synchronism with the instantaneous speed of the product retaining means; shift register means operatively coupled to said classifier circuit and to said means for providing the series of clock pulses, to receive said clock pulses and to generate an output pulse after a selected time delay proportional to the distance between the inspection chamber and the ejector means and determined by the rate of the series of clock pulses, the number of clock pulses being equal to the number of product retaining means disposed between the inspection chamber and said ejection means; and ejector driver means coupled to said shift register means for introducing a driver pulse to said ejector means in response to the occurrence of the output pulse from the shift register means.
 2. The memory system of claim 1 wherein the means associated with said succession of product retaining means further includes a slug of magnetic material precisely positioned relative to each of the succession of product retaining means, and magnetic pickup means fixedly disposed to sense the passage of the succession of slugs, and for generating a pulse commensurate with the time each slug passes adjacent the magnetic pickup means.
 3. The memory system of claim 1 wherein the means associated with said succession of product retaining means further includes a hole precisely positioned relative to each of the succession of product retaining means, light source means fixedly disposed to direct a beam of light through the succession of holes, and phototube means fixedly disposed to receive the light beam upon passage of each hole past the light source means and to generate said series of electrical pulses in synchronism with the speed of the product retaining means.
 4. The memory system of claim 1 wherein said means for providing a series of clock pulses includes amplifying and shaping means coupled to said means associated with said succession of product retaining means for delivering said number of clock pulses to said shift register means in response to the series of electrical pulses.
 5. The system of claim 4, wherein said shift register means include a plurality of bistable flip-flop circuits equal to the number of product retaining means disposed between the inspection chamber and the ejector means and connected in series, the flip-flop circuits being coupled to receive the series of clock pulses, wherein a first of the plurality of flip-flop circuits is further operatively coupled to said classifier circuit, and the last of the plurality of flip-flop circuits is operatively coupled to said ejector driver means.
 6. The system of claim 5, wherein said classifier circuit provides said reject pulse for subsequent introduction to the first flip-flop circuit when the inspection chamber senses a bad product to thus change the state of the first flip-flop wHereupon the successive flip-flop circuits change state at a rate determined by the successive introduction thereto of said number of clock pulses, said clock pulses being in synchronism with the instantaneous speed of the product retaining means, said last flip-flop circuit providing an output pulse upon changing state.
 7. The system of claim 1 wherein the means for providing a series of clock pulses further includes controllable timing means operatively coupled to said shift register means for delivering the series of clock pulses with a controllable time delay relative to the conveyed product.
 8. The system of claim 7 further including ejector pulse position controlling means coupled between the means for providing the series of clock pulses and the ejector driver means for controllably varying the initiation of the driver pulse relative to the preceding clock pulse.
 9. The system of claim 8 wherein the controllable timing means includes a pair of single-shot multivibrators coupled to receive the series of electrical pulses, gating means coupled to one of said single-shot multivibrators and also to said classifier circuit for delivering a reject output in response to said reject pulse from the classifier circuit and an output from the multivibrator, pulse shaping and amplifying means coupled to the second of the single-shot multivibrators and thence to the shift register means, said pair of single-shot multivibrators having means for controlling the time constants thereof wherein the time constants are maintained at a selected ratio over the controllable range.
 10. The system of claim 9, wherein the ejector pulse position controlling means includes a third single-shot multivibrator coupled to receive the series of clock pulses, and second gating means coupled to the shift register means and to the third single-shot multivibrator for introducing a single signal to said ejector driver means, said third single-shot multivibrator including means for controlling the time constant thereof wherein the signal delivered to the ejector driver means is selectively varied relative to the respective clock pulse. 